Apollo CMC

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Apollo Command Module Computer (CMC)

also known as

Apollo Guidance Computer (AGC)

Content

Hardware
1. AGC hardware modules
2. AGC logic modules
3. (To be added: info on core memory (RAM), core rope memory (ROM), integrated circuits (logic circuits, flip-flop registers?))
4. DSKY
Architecture and Instruction set
1. Block diagram of the AGC
2. Data and instruction format
3. Software stack
4. Address allocations for memory, registers and data channels
5. Channel assignments (To be checked on completeness)
6. Registers (To be checked on completeness)
7. Central processor control pulses
8. The native instruction set of the AGC (To be checked on completeness)
9. Organization of the code space for the native instruction order codes
10. The interpreter (virtual machine) instruction set (To be checked on completeness)
11. (To be added: Format of the interpreter instruction)
Navigation Software "Colossus" for the Apollo Command Module Computer
1. Navigation, Guidance & Control Programs
2. Routines
Title

1.Hardware


Figure 1.1
In the picture above the Apollo Guidance Computer and the user interface, the DSKY are shown. The computer consisted of two metal trays, tray A and tray B.Tray B was mountd on top of Tray A.


Figure 1.2
The two trays of the Apollo Guidance Computer containing the circuit modules. Tray A contained logic modules (24), interface modules (5) and power supplies. Tray B held the core rope memory modules (6), the driver circuitry for the core rope memory (4 modules), the erasable memory module (1), the circuitry to drive the erasable memory (4 modules), alarm circuits (1 module) and oscillator (1 module). The central processor was formed by most of the 24 logic modules. The whole logic circuitry was formed by 5,600 three-input NOR gates for which 4,100 integrated circuits were used. These three-input NOR gates were the building blocks for constructing data gates, flip-flops, which were the building blocks for the registers, the 16-bit adder, counters and the logic control circuitry. Table 1.1 contains a description of each logic module.

Logic Modules

	No.	Name	Purpose
1	A1	Scale Module	Manages frequency division and timing pulse generation.
2	A2	Timer	Handles timing and sequencing for computer operations.
3	A3	SQ Register and Decoding	To convert machine instructions into a sequence of control signals
4	A4	Stage Branch Decoding Module	Interpreting the current instruction opcode and directing the control logic to select the correct sequence of micro-operations (subsequences) for that instruction
5	A5	Cross Point Generator NQI	Decoding and switching matrix to manage 14 banks of relays, controlling the flow of data to and from the DSKY (Display and Keyboard) units, the Inertial Subsystem (ISS), the Optical Subsystem (OSS), and the Service Control System (SCS)
6	A6	Cross Point Generator II
7	A7	Service Gates	Managing data transfer between the central processor and the computer's registers
8	AB-II	4-bit Module	Part 1/4 of 16-bit Arithmetic Unit 4-bit X-register, Y-register, Adder and U-register
9	AB-II	4-bit Module	Part 2/4 of 16-bit Arithmetic Unit 4-bit X-register, Y-register, Adder and U-register
10	AB-II	4-bit Module	Part 3/4 of 16-bit Arithmetic Unit 4-bit X-register, Y-register, Adder and U-register
11	AB-II	4-bit Module	Part 4/4 of 16-bit Arithmetic Unit 4-bit X-register, Y-register, Adder and U-register
12	A12	Parity and S Register	The S register was a 12-bit memory address register that constructed the address for accessing both erasable (RAM) and fixed (ROM) (core rope) memory.

	No.	Name	Purpose
13	A13	Alarms	To alert the crew to system, software, or workload issues and to ensure the computer maintained control over critical tasks during critical phases of flight, such as the lunar landing
14	A14	Memory Timing and Addressing	To manage the flow of data between the processor and the two types of memory (RAM and Core Rope ROM)
15	A15	RUPT Service	To manage the computer's real-time, multi-tasking capabilities by immediately handling high-priority tasks and hardware events, ensuring the computer never lost control of the spacecraft
16	A16	INOUT I	Handling of I/O channels
17	A17	INOUT II	Handling of I/O channels
18	A18	INOUT III	Handling of I/O channels
19	A19	INOUT IV	Handling of I/O channels
20	A20	Counter Cell I	To manage high-speed, real-time input/output (I/O) data and timing functions without interrupting the main processor's execution of guidance and navigation software
21	A21	Counter Cell II
22	A22	INOUT V	Handling of I/O channels
23	A23	INOUT VI	Handling of I/O channels
24	A24	INOUT VII	Handling of I/O channels

Based on ref. 8

Table 1.1

Text

Text


Figure 1.3
The human interface of the Apollo Guidance Computer (AGC) also known as the Command Module Computer (CMC). With the DSKY the crew could iniiate programs, routines and enter data.

2.Architecture and Instruction set

TOPICS TO BE ADDRESSED

Various registers
Instruction formats
Memory management?
Evolution of the AGC during the mission phase of the Apollo program?
VERBS and NOUNS ?
Design considerations to meet requirements on size, weight, power consumption, functionality, maintainability, reliability, robustness, and ease of use?
(Dedicated computer design for navigation, guidance and control. Highly optimized computer architecture to minimize required program code to minimize required memory space and to optimize processor speed. Software stack design to minimize required memory space.)

Based on ref.2, figure 2-27

Figure 2.1

Text

Acronyms

AGC Apollo Guidance Computer
CDU Coupling Data Unit
CM Command Module
CMC Command Module Computer
DSKY Numeric Display and Keyboard
GDC Gyro Display Coupler
IMU Inertial Measurement Unit

ISS Inertial SubSystem (IMU, PIPA and CDU's)
OSS Optical SubSystem
PGNCS Primary Guidance Navigation and Control System
PIPA Pulsed Integrating Pendulous Accelerometer
RCS Reaction Control System
SCS Stabilization and Control System
SPS Service Propulsion System

Based on ref.1, figure VI-1 and ref.2, figure 2-21	Based on ref. 5 and ref.2
Figure 2.2	Table 2.1
Assembly code The AGC was not equipped with an assembler program to convert the assembly codes, expressed in mnemonics, into binary machine instructions. The conversion was done on mainframes. The binary machine instructions were then stored in the fixed memory of the AGC. To be more precise: the binary codes were handwoven into core rope memory. The Interpreter The Interpreter, also known as the AGC Virtual Machine, was in fact a collection of routines written in assembly code. The conversion, as well as the assembly mnemonics, was done on mainframes. The Interpreter was also stored in fixed memory. Programs and user routines The programs and the user routines were also stored in core rope memory. Those pieces of software were written in the interpreter language and the assembly language. The conversion of that software into binary code was done on mainframes as well. Conversion of machine instructions into control signals Programs, user routines and interpreter instructions ultimately resulted in a sequence of binary machine instructions which were presented to the Instruction Decoder. The Instruction Decoder and the Sequence Generator converted a binary machine instruction into a sequence of control signals to various relevant logic circuits to execute the instruction. This conversion process was executed using hardwired logic, which was composed of a set of thousands of identical 3-input NOR gates. Input directly to registers. The diagram shows that there was input passed via input logic which was hardware-interrupt-driven input sent directly to registers. There were eight registers which were located in erasable memory and acted as counters. The input was a sequence of digital pulses which were sent by the IMU and the optical subsystem to register incremental changes in the attitude, the velocity and the orientation of the optical subsystem. And there was one register (INLINK) to receive uplinked data. Interrupt-driven input via I/O channels. DSKY key entries passed an input channel. However, the reception of these entries by the AGC were also hardware-interrupt-driven.	A 12-bit address field was needed to address a core rope memory location, a 10-bit address field was needed to address a erasable memory location, and a 9-bit addressfiel was needed to address a I/O channel. An instructions with an 12-bit address field coould address a memory location in both memory types and could address a channel.


Figure 2.3
Note The diagram above has been derived from various descriptions of the AGC programs, routines, the operating system, the virtual machine, and the native assembly code. With this software stack I have tried to represent the relationships between the various entities as they appear in my mind. It helps to briefly picture how functionality has been organized in the AGC. Software stacks are a common way to show how software has been implemented in IT systems. The diagram might suggest that the Interpreter did not use all the available assembly code. That is, however, not correct. It has been drawn in this way to illustrate that routines and programs were written in interpreter language and in assembly language. Interface program "Pinball" This interface program handled the communication between the DSKY and the AGC. VERB and NOUN key entries were processed and sent as commands to the AGC. Data and prompts from the AGC were displayed in the 7-segment displays. The AGC could ask the crew for manual data input. The AGC prompted the crew by showing the applicable 2-digit VERB and NOUN codes. Numeric key entries were then sent as data to the AGC.	Routines, VERB and NOUN The crew had access to various functions and programs via routines. A specific routine could be initiated by entering a two digit VERB code and a two digit NOUN code via the DSKY. The verb referred to a specific action or command. The noun referred to specific data or parameters. For example, entering VERB 37 and NOUN 31 means initiate program (VERB 37) 31 (NOUN 31). "AGC Operating System" The "AGC Operating System" did have a somewhat different role than modern operating systems in which the machine code layer is totally shielded off from the software layers above. The routines and the programs could directly use the instructions of the virtual machine and the machine instructions. For example, the crew could directly access the Inertial Measurement Unit (IMU) using a routine. Although the "AGC OS" did not have total control over the AGC, it was able to closely monitor all the activities and manage all the operations in an orderly fashion using its interrupt and priority handling capabilities.

Address allocation

Address range (octal)			Type of address space	Purpose

Erasable memory (4 kbytes)
0000 \| 0007			Memory mapped address space of the unswitchabble erasable memory to address flip-flop registers and channels.	Central Registers
0010 \| 0061			This address range was used to accomodate registers in the erasable core memory. Was also used as memory-mapped address space to address channels.	Special Registers Counter Registers I/O Channels
0062 \| 0777			Memory mapped address space of the unswitchabble erasable memory to address channels. Was it also used as additional register space? For example: the R1, R2 and R2 registers for the DSKY?	I/O Channels Additional registers? Registers for the Virtual Machine?
1000 \| 1377			Remaining address space for the unswitchable erasable memory. 256 Address locations of 2 bytes (16 bits).	Data storage
Bank E0 1400 \| 1777	—————	Bank E6 1400 \| 1777	Bank switched erasable memory. 7 Banks, each bank had a capacity of 256 address locations of 2 bytes (16 bits).	Data storage

Fixed (core rope) memory (79 kbytes)
Bank 00 2000 \| 3777	—————	Bank 35 2000 \| 3777	Bank switched fixed memory. 36 Banks, each bank had a capacity of 1024 address locations of 2 bytes (16 bits).	Software storage
4000 \| 7777			Unswitchable fixed memory. 2,048 Address locations of 2 bytes (16 bits)	Software storage

Based on ref. X X X X X

Table 2.2

(Figure or Table)

Text

AGC Channel-Bit Assignments

Based on ref.4, page 12 and ref.9, table "Channel Bit Assignments"

Table 2.3

Note
The readings from the IMU, GDC (BMAGs), and the Optics Subsystem (OSS) were retrieved via the CDU data channels and were then directly sent to registers which acted as counters and were residing in erasable memory. The I/O channnels were not involved in retrieving the readings.

The name of registers which were related to the IMU and the OSS were: CDUX, CDUY, CDUZ, OPTY, OPTX, PIPAX, PIPAY, and PIPAZ. The registers that served as counters for the GDC (BMAG) readings are currently unknown to me. I need to check whether timer registers (TIME4, TIME5, and TIME6 ?) have been used as counters for the GDC (BMAG) readings.

The registers mentioned above were updated by a counter instruction which belonged to the category of involuntary instructions. This category of high priority instructions were inserted between the normal instruction cycles and enabled the AGC to receive measurements which were hardware interrupt driven.

Acronyms

BU Bus Management Unit
CDU Coupling Data Unit
CM Command Module
CMC Command Module Computer
IMU Inertial Measurement Unit
ISS Inertial SubSystem (IMU, PIPA and CDU's)
LM Lunar Module
LPD Landing Point Designator
L.R. Landing Radar
OSC Oscillator of the AGC
OSS Optical SubSystem
PIPA Pulsed Integrating Pendulous Accelerometer
PMA Processing Module Assembly
PMI Pitch Manual Input

RHC Rotation Hand Controller
RMC Rope Memory Core
RMI Roll Manual Input
R.R. Rendezvous Radar
RSS Radar SubSystem
S/C Spacecraft
SCT Scanning Telescope
SXT Sextant
THC Translation Hand Controller
YMI Yaw Manual Input

Registers

Method of access			Registers
Internally accessible by CP	Channel address (otcal)	Memory address (octal)	Physical form	Type	Name	Brief description
Yes			Integrated circuit	Internal	S	Memory Address Register. This register was holding the 12-bit memory address to read the content from a specific memory location in ROM or write/read to/from a specific memory location in RAM
Yes			Integrated circuit	Internal	G	Memory Buffer Register. Primary role: moving data between core memory and central processor.
Yes			Integrated circuit	Internal	X	Input register of the Arithmetic Adder
Yes			Integrated circuit	Internal	Y	Input register of the Arithmetic Adder
Yes			Integrated circuit	Internal	U	Output register of the Arithmetic Adder
Yes			Integrated circuit	Internal	B	General-purpose Buffer. Primary role: fetching instructions for the central procesor from core memory.
Yes			Integrated circuit	Internal	C	The 1's complement of the B register
Yes			Integrated circuit	Internal	SQ	Sequence Genarator Register. It held the instruction to be executed.
Yes			Integrated circuit	Internal	Cycle counter	A 5-bit register used to control shift instructions
Yes	00	00	Integrated circuit	Central	A	Accumulator
Yes	01	01	Integrated circuit	Central	L	lower product register
Yes	02	02	Integrated circuit	Central	Q	This register is intended to store return addresses of called procedures
Yes		03	Integrated circuit	Central	EB	Erasable bank register
Yes		04	Integrated circuit	Central	FB	fixed bank register
Yes		05	Integrated circuit	Central	Z	The program-counter register
Yes		06	Integrated circuit	Central	BB	both banks register
Yes		07	Stub	Central	(no name)	000 000 000 000
		10	Core memory	Work	ARUPT	This register is provided as a convenient location for storing the value of the A register during an interrupt service routine
		11	Core memory	Work	LRUPT	This register is provided as a convenient location for storing the value of the L register during an interrupt service routine.
		12	Core memory	Work	QRUPT	This register is provided as a convenient location for storing the value of the Q register during an interrupt service routine.
		13	Core memory	Work	SAMPTIME1	Register to store a copy of TIME1, as sampled in the waitlist interrupt service routine. Together with SAMPTIME2 it is used for Noun 65 displays.
		14	Core memory	Work	SAMPTIME2	Register to store a copy of TIME2, as sampled in the waitlist interrupt service routine. Together with SAMPTIME1 it is used for Noun 65 displays.
		15	Core memory	Work	ZRUPT	This register stores the return address, plus one, of an interrupt service routine.
		16	Core memory	Work	BBRUPT	This register is provided as a convenient location for storing the value of the BB register during an interrupt service routine.
		17	Core memory	Work	BRUPT	This register stores the value stored at the return address of an interrupt service routine.
		20	Core memory	Editing	CYR	The "cycle right register", which is one of the four so-called "editing" registers.
		21	Core memory	Editing	SR	The "shift right register", which is one of the four so-called "editing" registers.
		22	Core memory	Editing	CYL	The "cycle left register", which is one of the four so-called "editing" registers.
		23	Core memory	Editing	EDOP	The "edit polish opcode register", which is one of the four so-called "editing" registers.
		24	Core memory	Timer	TIME2	Upon overflow of TIME1, the 14-bit counter TIME2 is automatically incremented.
		25	Core memory	Timer	TIME1	TIME1 is a 15-bit 1's-complement counter which is incremented every 10 ms. The TIME1/TIME2 register pair acts as a 28-bit master clock for the AGC.
		26	Core memory	Timer	TIME3	TIME3 is a 15-bit 1's-complement counter which is incremented every 10 ms. It is incremented synchronously with TIME1.
		27	Core memory	Timer	TIME4	TIME4 is a 15-bit 1's-complement counter which is incremented every 10 ms.
		30	Core memory	Timer	TIME5	TIME5 is a 15-bit 1's-complement counter which is incremented every 10 ms. It is incremented 5 ms. out of phase with TIME1 and TIME3.
		31	Core memory	Timer	TIME6	TIME6 is a 15-bit 1's-complement counter which is updated every 1/1600 second by means of a DINC unprogrammed sequence.
		32	Core memory	Input	CDUX	Input register. Counter to monitor the orientation of the spacecraft. CDUX is referring to the inner gimbal angle of the IMU, which was aligned along the X-axis
		33	Core memory	Input	CDUY	Input register. Counter to monitor the orientation of the spacecraft. CDUY is referring to the middle gimbal angle of the IMU, which was aligned along the Y-axis
		34	Core memory	Input	CDUZ	Input register. Counter to monitor the orientation of the spacecraft. CDUX is referring to the outer gimbal angle of the IMU, , which was aligned along the Z-axis
		35	Core memory	Input	OPTY	Input register. Counter to monitor the orientation of the optics subsystem (i.e., the line of sight of the ACT and the SXT) or LM rendezvous radar with respect to the spacecraft. OPTY refers to the trunnion angle, around the Y-axis.
		36	Core memory	Input	OPTX	Input register. Counter to monitor the orientation of the optics subsystem (i.e., the line of sight of the ACT and the SXT) or LM rendezvous radar with respect to the spacecraft. OPTX refers to the shaft angle, around the X-axis.
		37	Core memory	Input	PIPAX	Input register. IMU related counter to monitor the velocity of the spacecraft in the X-direction
		40	Core memory	Input	PIPAY	Input register. IMU related counter to monitor the velocity of the spacecraft in the Y-direction
		41	Core memory	Input	PIPAZ	Input register. IMU related counter to monitor the velocity of the spacecraft in the Z-direction
		42	Core memory	Input	Q-RHCCTR (RHCP) "Pitch"	LM only. Input register. Counter to monitor the displacement of the rotational hand controller (RHC) in the PITCH axis.
		43	Core memory	Input	P-RHCCTR (RHCY) "Yaw"	LM only. Input register. Counter to monitor the displacement of the rotational hand controller (RHC) in the YAW axis.
		44	Core memory	Input	R-RHCCTR (RHCR) "Roll"	LM only. Input register. Counter to monitor the displacement of the rotational hand controller (RHC) in the ROLL axis.
		45	Core memory	Input	INLINK	Input register. This register is used to receive digital uplink data from a ground station.
		46	Core memory	Input	RNRAD	LM only Input register. This register is used to store data from the Rendezvous Radar and the Landing Radar.
		47	Core memory	Output	GYROCTR (GYROCMD)	Output register. Register "Gyro counter" (Gyro Counter) served as an input interface to IMU. It was used to during IMU fine alignment to torque the gyro to the the precise alignment expected by the AGC.
		50	Core memory	Output	CDUXCMD	Output register. Registers used during IMU coarse alignment to drive the IMU stable platform along the X-axis to approximately the orientation expected by the AGC.
		51	Core memory	Output	CDUYCMD	Output register. Registers used during IMU coarse alignment to drive the IMU stable platform along the Y-axis to approximately the orientation expected by the AGC.
		52	Core memory	Output	CDUZCMD	Output register. Registers used during IMU coarse alignment to drive the IMU stable platform along the Z-axis to approximately the orientation expected by the AGC.
		53	Core memory	Output	OPTYCMD	Output register. Register to send control signals for pointing the CM SXT and CM SCT or the LM R.R. around the Y-axis, i.e. controlling the trunnion angle.
		54	Core memory	Output	OPTXCMD	Output register. Register to send control signals for pointing the CM SXT and CM SCT or the LM R.R. around the X-axis, i.e. controlling the shaft angle.
		55	Core memory	Output	THRUST THRCMD	LM only Output register. Register to send control signals for controlling the throttle percentage of the Descent Propulsion System (DPS) engine during the lunar landing
		56	Core memory	Work	LEMONM	LM only Name of the register is an acronym for LEM Onboard Monitor. This register was used as a temporary storage location by the interpreter, which contained instructions (routines composed of native instructions) for complex calculations pertaining to orbital navigation. (---- needs to be checked ----)
		57	Core memory		OUTLINK	Not used Channel 34 and 35 were used to downlink data.
		60	Core memory	Input	ALTM	LM only Input register. Register to monitor the attitude and the altitude of the spacecraft based on data from the Landing Radar. The register provided readings to both the LGC programs and the crew displays.

With regard to the addressable registers: based on ref. 5

Table 2.4

Note
The way registers were accessible by the central processor (CP) is an example of the AGC's optimized design.
There were 9 registers which were internal to the CP and were directly accessible without the use of any address. These 9 registers were always flip-flop registers and could only be accessed by the CP.

S (Memory Address Register): a 12-bit register holding the memory address requested by the central computer;

G (Memory Buffer Register): a 16-bit register holding data words moving to and from memory;

X, Y, U (Arithmetic Registers): the X and Y registers held inputs for the adder, while U held the output of the 1's complement addition;

B (General-purpose Buffer): used to hold the next instruction to be executed; not directly addressable;

C: The 1's complement of the B register;

SQ (Sequence Register): a 4-bit register holding the current operation code (opcode) and;

the Cycle Counter: a 5-bit register used to control shift instructions

There were registers which were accomodated by the erasable core memory and not by flip-flop circuitry. These registers occupied far less physical space than the flip-flop registers. The design decision which registers should realized by using integrated circuits or core memory was determined by finding an optimal trade-off between speed and the required physical weight and cost. (During the development phase, the Apollo hardware and the S-II stage of the Saturn V rocket were periodically subjected to stringent weight-saving measures so as not to exceed the launch capacity of the Saturn V.)
The 3 registers (A, L and Q) of the 7 Central Registers (A, L, Q, EB, FB, Z and BB) were directly accessible for the CP and did have both a memory address and a channel address.
This construction was created:

to allow the CP to have fast direct access to these registers;
for efficient programming whereby a program could directly load data into the register by using a memory address and;

to allow data to be loaded directly into the registers which would act as data channels for which a channel address had to be used.

Control Pulses

1	A2X	Enter bits 16 through 1 of register A directly (not via WL's) into bit positions 16 through 1 of register X.
2	B15X	Enter a logic ONE into bit position 15 of register X.
3	Cl	Insert carry bit into bit position 1 of the adder.
4	CLXC	Clear register X if flip-flop BR1 contains a logic ZERO. (Used in divide instruction.)
5	DVST	Advance the Gray code content of the stage counter by complementing the content of the next higher bit position as shown below:
		Binary	Octal
		000	0
		001	1
		011	3
		111	7
		110	6
		100	4
6	EXT	Enter a logic ONE into bit position EXT of register SQ.
7	G2LS	Enter bits 16 through 4 and 1 of register G into bit positions 16, 15, and 12 through 1 of register X. See control pulse ZAP.
8	KRPT	Reset interrupt priority cells.
9	L16	Enter a logic ONE into bit position 16 of register L.
10	L2GD	Enter bits 16 and 14 through 1 of register L into bit positions 16 through 2 of register G; enter a logic ONE (pulse MCRO) into bit position 1 of register G.
11	MONEX	Clear register X, then enter logic ONE'S into bit positions 16 through 2.
12	MOUT	Generate one negative rate output pulse.
13	NEACOF	Permit end around carry upon completion of subinstruction MP3.
14	NEACON	Inhibit end around carry (also during WYD) until NEACOF.
15	NISQ	Load next instruction into register SQ. Also frees certain restrictions; permits execution of instruction RUPT and counter instructions. See control pulses RB and WSQ.
16	PIFL	Prevent interflow on control pulse WYD if bit position 15 of register L contains a logic ONE; block writing into bit position 1 of register Y. See control pulse WYD.
17	PONEX	Clear register X, then enter a logic ONE into bit position 1.
18	POUT	Generate one positive rate output pulse.
19	PTWOX	Clear register X, then enter a logic ONE into bit position 2.
20	R15	Place octal 15 on WL's.
21	R1C	Place octal 177776 (minus one) on WL's.
22	RA	Read bits 16 through 1 of register A to WL's 16 through 1.
23	RAD	Read address of next cycle. RAD appears at the end of an instruction and is normally interpreted as RG. If the next instruction is INHINT, RELINT, or EXTEND, RAD is interpreted as RZ and ST2 instead.
24	RB	Read bits 16 through 1 of register B to WL's 16 through 1.
25	RBBK	Read bits 16 and 14 through 11 of register FB to WL's 16 and 14 through 11 and bits 11, 10, and 9 of register EB to WL's 3, 2, and 1.
26	RBI	Place octal 1 on WL's.
27	RB1F	Place octal 1 on WL's if flip-flop BR1 contains a logic ONE.
28	RB2	Place octal 2 on WL's.
29	RC	Read the complemented contents of register B (bits 16 through 1 of C) to WL's 16 through 1.
30	RCH	Read the contents of the input or output channel specified by the contents of register S; bit 16 is read to WL's 16 and 15 and bits 14 through 1 are read to WL's 14 through 1.
31	REB	Read bits 11, 10, and 9 of register EB to WL's 11, 10, and 9. See control pulse RSC.
32	RFB	Read bits 16 and 14 through 11 of register FB to WL's 16 and 14 through 11. See control pulse RSC.
33	RG	Read bits 16 through 1 of register G to WL's 16 through 1.
34	RL	Read bit 16 of register L to WL's 16 and 15, and bits 14 through 1 to WL's 14 through 1.
35	RL10BB	Read low 10 bits of register B to WL's 10 through 1.
36	RQ	Read bits 16 through 1 of register Q to WL's 16 through 1.
37	RRPA	Place on WL's the address of the priority program requested.
38	RSC	Read the content of register CP defined by the content of register S; bits 16 through 1 are read to WL's 16 through 1.
39	RSCT	Place on WL's the address of the counter to be incremented.
40	RSTRT	Place octal 4000 (start address) on WL's.
41	RSTSTG	Reset the stage counter.
42	RU	Read bits 16 through 1 of adder output gates (U) to WL's 16 through 1.
43	RUS	Read bit 15 of adder output gates (U) to WL's 16 and 15, bits 14 through 1.
44	RZ	Read bits 16 through 1 of register Z to WL's 16 through 1.
45	ST1	Set stage 1 flip-flop to logic ONE at next time 12.
46	ST2	Set stage 2 flip-flop to logic ONE at next time 12.
47	STAGE	Execute next subinstruction as defined by the content of the divide stage counter.
48	TL15	Copy bit 15 of register L into flip-flop BR1.
49	TMZ	Test for minus zero: if bits 16 through 1 are all logic ONE'S, set flip-flop BR2 to logic ONE; otherwise set BR2 to logic ZERO.
50	TOV	Test for overflow: set flip-flops BR1 and BR2 to 01 if positive overflow, to 10 if negative overflow.

51	TPZG	Test content of register G for plus zero: if bits 16 through 1 are all logic ZERO'S, set flip-flop BR2 to logic ONE: otherwise do not change content of BR2.
52	TRSM	Test for the resume address (0017) during instruction NDX.
53	TSGN	Test sign (bit 16): if a logic ZERO, set flip-flop BR1 to logic ZERO; if a logic ONE, set flip-flop BR1 to logic ONE.
54	TSGN2	Test sign (bit 16): if a logic ZERO, set flip-flop BR2 to logic ZERO; if a logic ONE, set flip-flop BR2 to logic ONE.
55	TSGU	Test sign (bit 16) of sum contained in adder output gates (U): if a logic ZERO, set flip-flop BR1 to logic ZERO; if a logic ONE, set flip-flop BR1 to logic ONE.
56	U2BBK	Enter bits 16 and 14 through 11 of output gates U directly into regis¬ ter FB and bits 3, 2, and 1 of gates U into bits 11, 10, and 9 of register EB.
57	WA	Clear register A and write the contents of WL's 16 through 1 into bit positions 16 through 1.
58	WALS	Clear register A and write the contents of WL's 16 through 3 into bit positions 14 through 1; if bit position 1 of register G contains a logic ZERO, the content of bit position 16 of register G is entered into bit position 16 and 15 of register A; if bit position 1 of register G con¬ tains a logic ONE, the content of output gate U 16 of the adder is entered into bit positions 16 and 15 of register A; clear bits 14 and 13 of register L and write the contents of WL's 2 and 1 into bit positions
59	WB	Clear register B and write the contents of WL's 16 through 1 into bit positions 16 through 1.
60	WBBK	Clear registers EB and FB and write the content of WL's 16 and 14 through 11 into register FB and content of WL's 3, 2, and 1 into register EB. See control pulse WSC.
61	WCH	Clear the channel specified by the contents of register S (bits 9 through 1) and write the contents of WL's 16 through 1 into this channel.
62	WEB	Clear register EB and write the contents of WL's 11, 10, and 9 into bit positions 11, 10, and 9. See control pulse WSC.
63	WFB	Clear register FB and write the content of WL's 16 and 14 through 11 into bit position 16 and 14 through 11. See control pulse WSC.
64	WG	Clear register G and write the contents of WL's 16 through 1 into bit positions 16 through 1 (except if register S contains octal addresses
65	WL	Clear register L and write the contents of WL's 16 through 1 into bit positions 16 through 1.
66	WOVR	Test for positive overflow. If register S contains 0025, counter 0024 is incremented; if register S contains 0026, 0027, or 0030, instruction RUPT is executed.
67	WQ	Clear register Q and write the contents of WL's 16 through 1 into bit positions 16 through 1.
68	WS	Clear register S and write the contents of WL's 12 through 1 into bit positions 12 through 1.
69	WSC	Clear the CP register specified by the contents of register S and write the contents of WL's 16 through 1 into bit positions 16 through 1 of this register.
70	WSQ	Clear register SQ and write the contents of WL's 16 and 14 through 10 into bit positions 16 and 14 through 10, copy the content of the extend flip-flop into bit position EXT of register SQ. See control pulse NISQ.
71	WY	Clear registers X and Y; write the contents of WL's 16 through 1 into bit positions 16 through 1 of register Y.
72	WY12	Clear registers X and Y; write the contents of WL's 12 through 1 into bit positions 12 through 1 of register Y.
73	WYD	Clear registers X and Y; write the contents of WL's 16 and 14 through 1 into bit positions 16 and 15 through 2 of register Y; write the content of WL 16 into bit position 1 of register Y except in SHINC sequence, or unless bit 15 of register L is a logic ONE at PIFL, or if end around carry is inhibited (NEACON).
74	WZ	Clear register Z and write the contents of WL's 16 through 1 into bit positions 16 through 1.
75	Z15	Enter a logic ONE into bit position 15 of register Z.
76	Z16	Enter a logic ONE into bit position 16 of register Z.
77	ZAP	Generate control pulses RU, G2LS, and WALS.
78	ZIP	Generate control pulses A2X and L2GD; also perform read/write operations depending on the content of bit positions 15, 2, and 1 of register L as shown:
		L15	L2	L1	Read	Write	Carry	Remember
		0	0	0	- - -	WY	- - -	- - -
		0	0	1	RB	WY	- - -	- - -
		0	1	0	RB	WYD	- - -	- - -
		0	1	1	RC	WY	Cl	MCRO
		1	0	0	RB	WY	- - -	- - -
		1	0	1	RB	WYD	- - -	- - -
		1	1	0	RC	WY	Cl	MCRO
		1	1	1	- - -	WY	- - -	MCRO
79	ZOUT	Generate no rate output pulse.

Based on ref.2, figure 4-VI

Table 2.5

Control pulses for executing machine instructions
Programs, routines and Virtual Machine (interpreter) instructions resulted in a sequence of assembly codes (machine instructions). Each machine instruction was converted by the Instruction Decoder in conjunction with the Sequence Generator into a sequence of control pulses over 12 time intervals, each with a duration of 11.7 microseconds. These 12 time intervals corresponded with one machine cycle.

Text

The Native Instruction set of the AGC

1. SEQUENCE CHANGING (regular instructions)
Transfer control	TC K	Transfer control	Basic instruction; takes next instruction from K; stores I+1 in Q where I is location of TC K; if K is 0006(OCT) (EXTEND), sets extracode switch and takes next instruction from I+1; if K is 0004(OCT) (INHINT) sets inhibit interrupt switch and takes next instruction from I+1; if K is 0003(OCT) (RELINT), resets inhibit interrupt switch and takes next instruction from I+1.
Transfer control	TCF F	Transfer control to fixed memory	Basic instruction; takes next instruction from F.
Decision making	CCS E	Count, compare, and skip	Basic instruction; if c(E) is non-zero and positive, takes next instruction from I+1 where I is location of CCS E. Also, adds -1 to c(E) and stores result in A. If c(E) is +0, takes next instruction from I+2 and sets c(A) to +0. If c(E) is non-zero and negative, takes next instruction from I+3, adds -1 to c(E), and stores result in A. If c(E) is -0, takes next instruction from I+4 and sets c(A) to +0.
	BZF F	Branch on zero to fixed memory	Extracode instruction; takes next instruction from F if c(A) is +0; otherwise takes next instruction from I+1 where I is location of BZF F.
	BZMF F	Branch on zero or minus to fixed memory	Extracode instruction; takes next instrution from F if c(A) is +0 or negative; otherwise takes next instruction from I+1 where I is location of BZMF F.
2. FETCHING AND STORING (regular instructions)
Copying	CA K	Clear and add	Basic instruction; copies c(K) into A; takes next instruction from I+1 where I is location of CA K.
	CS K	Clear and subtract	Basic instruction; copies c(K) into A; takes next instruction from I+1 where I is location of CS K.
	DCA K	Double precision clear and add	Extracode instruction; copies c(K, K+l) into A and L; takes next instruction from I+1 where I is location of DCA K.
	DCS K	Double precision clear and subtract	Extracode instruction; copies c(K, K+l) into A and L; takes next instruction from I+1 where I is location of DCS K.
Storing	TS E	Transfer to storage	Basic instruction; if c(A) is not an over¬ flow quantity, copies c(A) into K and takes next instruction from I+1 where I is location of TS K; if c(A) is a positive overflow quantity, copies c(A) into K, sets c(A) to +1, and takes next instruction from I+2; if c(A) is a negative overflow quantity, copies c(A) into K, sets c(A) to -1, and takes next instruction from I+1.
Exchange	XCH E	Exchange A	Basic instruction; exchanges c(A) with c(E); takes next instruction from I+1 where I is location of XCH E.
	QXCH E	Exchange Q	Extracode instruction; exchanges c(E) with c(L); takes next instruction from I+1 where I is location of QXCH E.
	LXCH E	Exchange L	Basic instruction; exchanges c(E) with c(L); takes next instruction from I+1 where I is location of LXCH E.
	DXCH E	Double exchange	Basic instruction; exchanges c(E, E+1) with c(A, L); takes next instruction from I+1 where I is location of DXCH E.
3. MODIFYING (regular instructions)
Indexing	NDX E	Index basic	Basic instruction; adds c(K) to c(I+1) where I is location of NDX E; takes sum of c(K) + c(I+1) as next instruction.
Indexing	NDX K	Index extracode	Extracode instruction; adds c(K) to c(I+1) where I is location of NDX K; sets extra code switch; sum of c(K) + c(I+1) becomes an extracode instruction which is taken as next instruction.
4. ARITHMETIC AND LOGIC (regular instructions)
Arithmetic	AD K	Add	Basic instruction; adds c(K) to c(A); stores result in A; takes next instruction from I+1 where I is location of AD K.
	SU E	Subtract	Extracode instruction; subtracts c(A) from c(E); stores result in A; takes next instruction from I+1 where I is location of SU E.
	MP K	Multiply	Extracode instruction; multiplies c(A) by c(E); stores result in A and L; c(A, L) agree in sign; takes next instruction from I+1 where I is location of MP E.
	DV E	Divide	Extracode instruction; divides c(A, L) by c(E); stores quotient in A; stores remainder in L; takes next instruction from I+1 where I is location of DV E.
Adding and storing	ADS E	Add and store	Basic instruction; adds c(A) to c(E) and stores result in both A and E; takes next instruction from I+1 where I is location of ADS E.
Adding and storing	DAS E	Double precision add and store	Basic instruction; adds c(A, L) to c(E, E+1); stores result in E and E+1; sets c(L) to +0 and sets c(A) to net overflow if address E is not 0000(OCT). Net overflow is +1 for positive overflow, -1 for negative overflow, otherwise c(A) is set to +0. Takes next instruction from I+1 where I is location of DAS E.
Incrementing	INCR E	Increment	Basic instruction; adds +1 to c(E); stores result in E; takes instruction from I+1 where I is location of INCR E.
	AUG E	Augment	Extracode instruction; adds +1 to \|c(E)\|, i.e., adds +1 if c(E) is positive and -1 if c(E) is negative; stores result in E; takes next instruction from I+1 where I is location of AUG E.
	DIM E	Diminish	Extracode instruction; adds -1 to \|c(E)\|, i.e., adds -1 if c(E) is non-zero and positive and +1 if c(E) is non-zero and negative; stores result in E; takes next instruction from I+1 where I is location of DIM E.
Angular subtraction	MSU E	Modular subtract	Extracode instruction; forms the signed one's complement difference between c(A) and c(E) where c(A) and c(E) are unsigned (modular or periodic) two's complement numbers; stores result in A; takes next instruction from I+1 where I is location of MSU E.
Logic	MSK K	Mask or AND	Basic instruction; AND's c(A) with c(K); stores result in A; takes next instruction from I+1 where I is location of MSK K.
5. INPUT-OUTPUT (regular instructions)
Read	READ H	Read channel	Channel instruction; copies c(H) into A; takes next instruction from I+1 where I is location of READ H.
	RAND H	Read and AND	Channel instruction; AND's c(H) with c(A); stores result in A; takes next instruction from I+1 where I is location of RAND H.
	ROR H	Read and OR	Channel instruction; OR's c(H) with c(A); stores result in A; takes next instruction from I+1 where I is location of ROR H.
	RXOR H	Read and EXCLUSIVE OR	Channel instruction; forms the exclusive OR of c(H) and c(A); stores result in A; takes next instruction from I+1 where I is location of RXOR H.
Write	WRITE H	Write channel	Channel instruction; copies c(A) into H; takes next instruction from I+1 where I is location of WRITE H.
	WAND H	Write and AND	Channel instruction; AND's c(H) with c(A); stores result in H and A; takes next instruction from I+1 where I is location of WAND H.
	WOR H	Write and OR	Channel instruction; OR's c(H) with c(A); stores result in H and A; takes next instruction from I+1 where I is location of WOR H.

6. EDITING (regular instructions)
Control	RELINT	Release interrupt inhibit	Special instruction; see TC K.
	INHINT	Inhibit interrupt	Special instruction; see TC K.
	EXTEND	Extend order code field	Special instruction; see TC K.
	RESUME	Resume interrupted program	Special instruction; takes next instruction from return address.
Shift and cycle	CYR	Cycle right	Special instruction; cycles quantity, which is entered into location 0020, one place to right.
	SR	Shift right	Special instruction; shifts quantity, which is entered into location 0021, one place to right.
	CYL	Cycle left	Special instruction; cycles quantity, which is entered into location 0022, one place to left.
	EDOP	Edit operator	Special instruction; shifts quantity, which is entered into location 0023, seven places to left.
7. PRIORITY (involuntary instructions)
Interrupt	RUPT F	Interrupt	Interrupting instruction; takes next instruction from location F; stores c(B) (instruction that was to be executed) in location 0017(OCT); stores c(Z) = I in location 0015(OCT), where I is assigned location of instruction stored in 0017(OCT).
Interrupt	GOJ F	Start	The GOJ (Go and Jump) instruction in the Apollo Guidance Computer (AGC) was a specialized, unconditional jump instruction used to jump to a new memory address while storing the return address in the accumulator. It was used to implement subroutines efficiently, particularly within the assembler code that managed the transition between assembly language and the "interpretive" language, which was used for complex guidance calculations.
Counter	PINC C	Plus increment	Counter instruction; adds +1 to c(C); delays program execution for 1 MCT. C refers to an address of one of the 12 registers (T1 - T6, PIPAX, PIPAY, PIPAZ, BMAGX, BMAGY, BMAGZ) which were residing in RAM and acted as time counters, counters to monitor the velocity of the spacecraft (based on PIPA/IMU data) and the orientation of the spacecraft (based on BMAG data)
	MINC C	Minus increment or decrement	Counter instruction; adds -1 to c(C); delays program execution for 1 MCT. C refers to an address of one of the 6 registers (PIPAX, PIPAY, PIPAZ, BMAGX, BMAGY, BMAGZ) which were residing in RAM and acted as counters to monitor the velocity of the spacecraft (based on PIPA/IMU data) and the orientation of the spacecraft (based on BMAG data)
	DINC C	Diminish increment	Counter instruction; adds +1 to c(C) if c(C) is negative and provides negative rate output pulses; adds -1 to c(C) if c(C) is positive and provides positive rate output pulses; provides no rate output pulses when c(C) is ±0; stores result in C; delays program execution for 1 MCT. C refers to an address of one of the 8 output registers (GYRO, CDUXCMD, CDUYCMD, CDUZCMD, OPTXCMD, OPTYCMD, THRUST, LEMONM) which were residing in RAM and acted as data registers to align the IMU, to point the optics subsystem and to throttle the LM desecent engine.
	PCDU C	Increment CDU	Counter instruction; adds +1 (two's complement) to c(C); delays program execution for 1 MCT. C refers to an address of one of the 5 registers (CDUX, CDUY, CDYZ, OPTX, and OPTY) which were residing in RAM and acted as counters to monitor the orientation of the spacecraft (based on IMU data) and the orientation of the optics subsystem.
	MCDU C	Decrement CDU	Counter instruction; adds -1 (two's complement) to c(C); delays program execution for 1 MCT. C refers to an address of one of the 5 registers (CDUX, CDUY, CDYZ, OPTX, and OPTY) which were residing in RAM and acted as counters to monitor the orientation of the spacecraft (based on IMU data) and the orientation of the optics subsystem.
	SHINC C	Shift increment	Counter instruction; doubles c(C); stores result in C; delays program execution for 1 MCT.
	SHANC C	Shift add increment	Counter instruction; doubles c(C) and adds +1; stores result in C; delays program execution for 1 MCT.
8. PERIPHERAL (used for pre-launch testing of AGC)
Transfer control	TCSAJ K	Transfer control to specified address	Peripheral instruction; takes next instruction from K where K is address supplied by CTS (Computer Test Set).
Read	FETCH K	Read memory	Peripheral instruction; reads and displays c(K) as binary numbers on CTS, where K is address supplied by CTS.
Read	INOTRD H	Read channel	Peripheral instruction; reads and displays c(H) as binary number on CTS, where H is channel address supplied by CTS.
Load	STORE E	Load memory	Peripheral instruction; data supplied by CTS is stored in location E where E is address supplied by CTS; delays program execution for 2 MCT's.
Load	INOTLD H	Load channel	Peripheral instruction; loads data supplied by CTS into location H, where H is channel address also supplied by CTS.

Address Indications
K	any address
E	erasable memory address
F	fixed memory address
C	counter address
H	channel address
CP	central processor address

Conventions
c(K)	value at address K
c(A)	value in central accumulator
c(L)	value in lower accumulator

Based on ref.2, figures 4-II and 4-IV

Table 2.6

A list of 56 machine instruction or native instructions
This set of machine instructions, together with the configuration of the AGC hardware and the hardware control logic, defined the architecture of the AGC.
The machine instructions were contained in the hardwired control logic. All program, routine and interpreter instructions resulted in a sequence of machine instructions which were presented to the Instruction Decoder (figure 1.1). In conjunction with the Sequence Generator, the Instruction Decoder converted the instructions into control signals for executing the instructions. Both functional components were part of the control logic.

Text

Organization of the code space for the instruction order codes

Based on ref.5 and ref.6

Table 2.7

Table 2.8

A 12-bit address field was needed to address a core rope memory location, a 10-bit address field was needed to address a erasable memory location, and a 9-bit addressfiel was needed to address a I/O channel.
An instructions with an 12-bit address field could address a memory location in both memory types and could address a channel.

How the code space for order codes was organized
The table above provides an overview of how order codes were assigned to the various instructions which always had a word lenght of 15 bits.

A basic 15-bit instruction word contained an order code which was 3 bits long, accomodated by bit 15, 14, and 13. This 3-bit basic instruction was called an opcode (operation code) |C|C|C|, which accomodated a maximum of 8 instructions. This number was insufficient by far to use the available functionality of the central prcocessor efficiently and effectively.

Methods to enlarge the code space for the order code
To increase the instruction set several methods were used to increase the code space for instructions.

The extra code flag
To equip the instruction decoder with a extra code flag to enable the decoder to interpret the 3-bit opcode in two ways. It was a way to virtually add a fourth bit to the 3-bit order code and increase the code space by a factor of 2.
A separate instruction (EXTEND) was needed to set the flag to instruct the decoder to interpret the 3-bit opcode in the alternative way. The flag was reset automatically after the execution of the instruction.
Using some higher bits of the address field as extensions of the order code
To use the higher bits of the address field to extent the opcode. This was possible because a 12-bit address space was not always required to address a memory location or and I/O channel.
To address a ROM (core rope memory) location a 12-bit address space was required. So instructions in which ROM memory locations needed to be addressed, had a 3-bit the order code:
|C|C|C|
To address a RAM (erasable memory) loaction a 10-bit address space was required. For instructions in which RAM memory locations needed to be addressed, the 3-bit order code could be extended with a 2-bit quarter code (QC):
|C|C|C|Q|Q|
To address a I/O channel a 9-bit address space was required. For instructions in which an I/O channel needed to be addressed, the 3-bit order code could be extended with a 3-bit peripheral code (PC):
|C|C|C|P|P|P|
The methodology of addressing instructions is shown above.
The addressing methodology was incorporated in the logical design of the instruction decoder. It enabled the decoder, by evaluating the 3-bit order code, to infer whether extensions of the 3-bit order code were applicable.
When the extra code flag is not set, and the opcode of the instruction is 2 or 5, then bits 12 and 11 of the instruction word must be considered as a 2-bit extension of the 3-bit order code.
When the extra code flag is set by the EXTEND instruction, and the opcode of the instruction is 2, then bits 12 and 11 of the instruction word must be considered as a 2-bit extension of the 3-bit order code. But when the opcode of the instruction is 0, then bits 12. 11, and 10 of the instruction word must be considered as a 3-bit extension of the 3-bit order code.
The decoder also evaluated the 12-bit address field. When the opcode was 1 in the case that extra code flag was not set and 1 or 6 in the case that the extra code flag is set, and the bits 12 and 11 were both 0, then these bits must be considerd as a 2-bit quarter code. If one of these bits or both were not both 0 than the instruction must be considered as a 3-bit order code with a 12-bit address field.
Using the lower bits of the address field as extensions of the order code
This method was used for instructions which didn't have an operand. That means that, in principle the bits 1 up to 9 of the address field were available for coding instructions wtihout an operand. However in order to enable the instruction decoder to conclude whether the operand was referring to a memory location or must be interpreted as an extension of the order code, only the address range 0000 (OCT) - 0007 (OCT) was used as extension codes. So an instruction word with format 00•000A (OCT) was processed as an instruction with no operand. On the other hand, an instruction word with format 00•AAAA (OCT) was processed as an instruction (opcode 0 is referring to instruction TC) with an operand referring to memory address AAAA.
(The preceding red 0 represents the status of the extra code flag. That bit is 1 when the flag is set.)
For example, if the extra code flag was not set, the decoder was instructed to use the the lower 3 bits of the address field as extensions of the order code 000 (0 (OCT)). When the operand (address field) was 0006 (OCT) then instruction word 00•0006 (OCT) must be interpreted as an EXTEND instruction, the instruction which was used to set the extra code flag.

Methods of order code extensions explained

Based on ref.5 and ref.6

Table 2.9

In the tables above is stepwise shown how the code space for the order code was enlarged to increase the number of instructions. There were cases in which the 12-bit operand field or the address field could be partly used as extensions of the order code because the 12-bit address space was not always needed. Three categories of AGC central processor peripherals could be distinguished: the ROM, the RAM and the data channels, which included the 31 I/O channels. The ROM was 18 times larger than the RAM. To address a memory location in ROM, a 12-bit address was needed. To address a memory location in RAM a 10-bit address was needed. To address a data channel, 9 bits were needed to accommodate a maximum of 512 data channels, which was more than enough.
Therefore, three categories of instructions could be distinguished according to the size of their operand size: 12, 10 or 9 bits.

In the tables above is shown how the three categories of instructions are classified by their opcode.

The absolute maximum number of instructions with 12-bit operands was 16 if each instruction must be able to target all memory locations from 0000 (OCT) to 7777 (OCT). In principle it was possible to increase this number of instructions significantly by introducing a mechanism in which each instruction was only allowed to address a limited range of addresses. The downside of this approach was that instructions may not be able to share data with other instructions via memory because they are not able to share the same memory address space. It was possible to share data via the processor registers. But this would have had a severe impact on the processor performance because its registers would not only be used for control and for arithmetic operations but also to manage the data-sharing between the instructions. This approach would have complicated the architecture and the programming.
So opcode-specific distinctions between categories of instructions would not introduce these data-sharing problems. However, instructions with 12-bit operands were able to address memory locations in ROM and RAM. Instructions with 10-bit operands were only able to address memory locations in RAM.

In table 2.9.4 an arrangement is shown in which there are 11 instructions with 12-bit operands, 16 instructions with 10-bit operands, and 8 instructions with 9-bit operands.
Table 2.9.5 shows an arrangement in which the number of instructions with 10-bit operands has been increased from 16 to 20 while maintaining the number of 11 instructions with 12-bit operands. The consequence is that these instructions with 12-bit operands which have the same opcode as the instructions with 10-bit operands can only cover the 12-bit address range from 1000 (OCT) to 7777 (OCT); the address range from 0000 (OCT) to 0777 (OCT) is not accessible. The RAM address range was 0000 (OCT) - 1777 (OCT). The ROM address range was 2000 (OCT) - 7777 (OCT). It means that these instructions could partly cover the RAM but could completely cover the ROM.

(A selection of) The Interpreter (Virtual Machine) Instruction set of the AGC

1. SCALAR ARITHMETIC
ABS	Absolute value
BDSU	Reverse double-precision subtraction.
DADD	Double precision addition
DDV	Double precision divide
DMP	Double precision multiply
DSUB	Double precision subtraction
ROUND	Round a double-precision number to single precision
SADD	Single precision addition
SDV	Single precision divide
SIGN	Apply sign of one value to another
SMP	Single precision multiply
SSUB	Single precision subtraction
TADD	Triple precision addition
TSUB	Triple precision subtraction
2. VECTOR/SCALAR ARITHMETIC
PROJ	Vector Projection
UNIT	Normalize a Vector (Unit Vector)
VAB	Vector Absolute Value (Magnitude)
VADD	Vector addition
VDOT	Vector dot-product
VDV	Vector-Scalar Division
VMP	Vector-Scalar Multiplication
VSL	Vector shift left
VSR	Vector shift right
VSUB	Vector subtraction
VXV	Vector cross-product
3. MATRIX OPERATIONS
MXV	Matrix multiplied by Vector
VXM	Vector multiplied by Matrix
4. MATHEMATICAL FUNCTIONS
ARCCOS	Arccosine
ARCSIN	Arcsine
ATAN	Arctangent
COS	Cosine
SIN	Sine
SQRT	Square root
TAN	Tangent

5. LOADING AND STORING
DLOAD	Double precision load
DSTOR	Double precision store
LOAD	Load a scalar
SET	Set a flag/variable
SLOAD	Single precision load
SSTOR	Single precision store
STODL	Store and then load double precision
STORE	Store a scalar
STOVL	Store and then load a vector
VLOAD	Load vector into MPAC
VSTOR	Store vector from MPAC
6. PROGRAM CONTROL & FLOW CONTROL
BHJ	Branch if Higher or Jump
BLJ	Branch if Lower or Jump
BMI	Branch if minus
BNZ	Branch if Not Zero
BPL	Branch if plus
BVS	Branch if vector sign
BZE	Branch if zero
CALL	Call an interpreter subroutine.
CLEAR	Clear MPAC ( Set a flag/variable to zero)
EXIT	Leave interpreter mode and return to native code.
GOTO	Unconditional jump within the interpretive code
INTPRET	Call the interpreter (start interpreting).
RTN	Return from interpreter subroutine.

Based on X X X X X

Table 2.10

Interpreter instructions are routines composed of native instructions
In the table above, only 57 of the approximately 128 interpreter instructions are shown.
These interpreter instructions can be considered as routines composed of the native machine instructions. A set of 42 of a total of 56 native instructions could be used to construct interpreter instructions. The other 14 native instructions from the categories PRIORITY and PERIPHERAL were not designed to be used for programming. The interpreter instructions contained complex mathematical functions. These interpreter instructions made it more efficient for programmers to develop navigation, guidance & software. It also saved a lot of memory space.

Storage in core rope memory
The interpreter instructions were stored in fixed memory. These fixed memories were made using electric wires which were handwoven through and around tiny magnetic rings. A wire through a ring represented a binary 1, and a wire bypassing a ring represented a binary 0. Multiple wires were woven through and around the rings. As a result, one ring was used to constitute multiple bits. A very efficient way to store information.

Text

3.Navigation Software "Colossus" for the Apollo Command Module Computer

AGC Navigation, Guidance & Control Programs

		Incorporated routines
Prelaunch and Service
P00	CMC idling
P01	Prelaunch or service - initialization
P02	Prelaunch or service - gyro compassing
P03	Prelaunch or service - optical verification of gyro compassing
P05	GNCS Startup
P06	GNCS power down
P07	IMU performance test
Boost
P11	Earth Orbit Insertion (EOI) Monitor
P15	Trans Lunar Injection (TLI) Initiate/Cutoff
Coast
P20	Rendezvous Navigation	R02, R22, R52, R61, R67
P21	Ground Track Determination
P22	Orbital Navigation	R02, R52
P23	Cislunar Midcourse Navigation	R52, R53, R57, R60
P24	Rate-aided optics (landmark tracking)
P27	CMC Update
P29	Preferred Tracking Attitude
Targeting and setting pre-thrust conditions
P30	External Delta-V for trajectory change
P31	Height Adjustment Maneuver (HAM)
P32	Co-elliptic Sequence Initiate (CSI)
P33	Constant Delta altitude (CDH)
P34	Transfer Phase Initiation (TPI)
P35	CSM Transfer Phase Midcourse (TPM) Targeting
P36	Plane Change (PC) Targeting
P37	Return To Earth (RTE)
P38	Stable Orbit Rendezvous (SOR), Delta-V for Rendezvous
P39	Stable Orbit Midcourse (SOM)

		Incorporated routines
Thrust
P40	SPS	R41
P41	RCS	R41
P47	Thrust Monitor	R41
IMU Alignment
P51	IMU Orientation Determination	R53, R54
P52	IMU Realign	R02, R50, R51
P53	Backup IMU Orientation Determination	R56
P54	Backup IMU Reallgn	R02, R50, R51
Entry
P61	Entry Maneuver to CM/SM Separation Attitude	R02, R41
P62	CM/SM Separation & Pre-entry maneuver	R02
P63	Entry - Initialization
P64	Post .05 G
P65	Entry - up control
P66	Entry - ballistic
P67	Entry Final Phase
Targeting
P72	LM Co-elliptic Sequence Initiation (CSI) targeting
P73	LM Constant Delta altitude (CDH) targeting
P74	LM Transfer Phase Initiation (TPI) targeting
P75	LM transfer phase (midcourse) targeting
P76	LM target Delta V
P77	CSM target Delta V
P78	SOR Targeting
P79	Rendezvous final phase

Based on X X X X X

Table 3.1

Storage in core rope memory
Programs were stored in fixed memory. These fixed memories were made using electric wires which were handwoven through and around tiny magnetic rings. A wire through a ring represented a binary 1. and a wire bypassing a ring represented a binary 0. Multiple wires were woven through and around the rings. As a result, one ring was used to constitute multiple bits. A very efficient way to store information.

Text

AGC Routines

		User
R00	Final automatic request terminate
R01	Erasable and channel modification routine	Crew	V25N07
R02	IMU status check	Programs Routines	P20, P22, P40, P47, P52, P54, P61, P62 R05, R63
R03	Digital autopilot data load	Crew	V48
R05	S-Band antenna angles	Crew	V64
R07	MINKEY Controller		----- To be checked -----
R21	Rendezvous tracking sighting mark	Crew	V57
R22	Rendezvous tracking data processing	Programs	P20
R23	Backup rendezvous tracking and sighting mark	Crew	V54
R30	Orbit parameter display	Crew	V82
R31	Orbit parameter display number one	Crew	V83
R32	Target Delta V	Crew	V84
R33	CMC/LGC clock synchronization	Crew	V06N65
R34	Rendezvous parameter display number two	Crew	V85
R36	Rendezvous out-of-plane display	Crew	V90
R40	SPS thrust fail	Programs	P40
R41	State vector integration (MID to AVE)	Programs	P40, P41, P47, P61
R50	Coarse align	Programs	P52, P54
R51	Fine align	Programs	P52, P54
R52	Automatic optics positioning	Programs Routines	P20, P22, P23 R51
R53	Sighting mark	Programs Routines	P23, P51, R52
R54	Sighting data display	Programs Routines	P51 R51
R55	Gyro torquing	Routines	R51
R56	Alternate LOS sighting mark	Programs Routines	P53 R51
R57	Optics calibration	Program	P23
R60	Alternate LOS sighting mark	Programs Routines Crew	P23, P40 R61, R62 V89
R61	Tracking attitude	Programs Routines	P20 R52
R62	Crew defined maneuver	Crew	V49
R63	Rendezvous final attitude	Routine Crew	R61 V89
R64	Barbecue mode routine	Crew	V79
R67	Universal pointing	Programs	P20

Based on X X X X X

Table 3.2

Routines used by end-users, programs and other routines
The routines mentioned in the table above were of a different category than the routines of the peudo insrtctions mentioned in table 1.3. These routines mentioned in table 2.2 were small programs, blocks of instructions to perform a specific task. There were routines which could be used by an user, various programr or various other routines.

V25N07 means VERB 25 - NOUN 07

Title

- - - - TABLE - - - -

Based on X X X X X

Table 3.3

Text

4.Title


Figure 4.1 Text	Figure 4.2 Text


Figure 4.3 Text

Acronyms

AGC Apollo Guidance Computer
BU Bus Management Unit
BMAG Body Mounted Attitude Gyro
CDH Constant Delta Altitude
CDU Coupling Data Unit
CMC Command Module Computer
CMC Command Module Computer
CSI Co-elliptic Sequence Initiate
CTS Computer Test Set
EOI Earth Orbit Insertion
GDC Gyro Display Coupler
GNCS Guidance, Navigation & Control System
HAM Height Adjustment Maneuver
IMU Inertial Measurement Unit
ISS Inertial SubSystem (IMU, PIPA and CDU's)
LOI Lunar Orbit Insertion
LPD Landing Point Designator
L.R. Landing Radar

OSC Oscillator of the AGC
OSS Optical SubSystem
PC Plane Change
PGNCS Primary Guidance Navigation & Control System
PIPA Pulsed Integrating Pendulous Accelerometer
PMA Processing Module Assembly
PMI Pitch Manual Input
RHC Rotation Hand Controller
RMC Rope Memory Core
RMI Roll Manual Input
R.R. Rendezvous Radar
RTE Return To Earth
S/C Spacecraft
SOM Stable Orbit Midcourse
SOR Stable Orbit Rendezvous
THC Translation Hand Controller
TLI Trans Lunar Injection
TPI Transfer Phase Initiation
YMI Yaw Manual Input

References

Apollo Guidance and Navigation
R-500 Space Navigation Guidance and Control
Volume 2 of 2
MIT Instrumentation Laboratory
Cambridge, Massachusetts, June 1965
Project Apollo
Apollo Lunar Excursion Module
Primary Guidance, Navigation, and Control System
Manual Volume I of II
ND-1021042
Prepared for NASA, Manned Spacecraft Center
Prepared by AC Electronics Division of General Motors
Milwaukee, Wisconsin 53201, 1 February 1966
Apollo Training
Guidance and Control Systems Block II, Spacecraft 101
Apollo Logistics Training
North American Aviation (NAA)
Space and Information Systems Division (S&ID)
Downey, California, 15 September 1967
The Virtual AGC Project Spaceborne Computer Systems
The Block I AGC in all its Aspects
https://www.ibiblio.org/apollo/Block1.html#gsc.tab=0
The Virtual AGC Project Spaceborne Computer Systems
Programmer's Manual
Block 2 AGC Assembly Language
https://www.ibiblio.org/apollo/assembly_language_manual.html#gsc.tab=0
AGC4 MEMO # 9 - Block I1 Instructions
By Hugh Blair-Smith
September 30 1965, Revised July 1 1966
Massachusetts Institute of Technology
Instrumentation Laboratory
Cambridge, Massachusetts
APOLLO GUIDANCE COMPUTER
BLOCK II – CMC DATA CARDS
A compilations of information from original Apollo AGC data cards
Compiled by: Fabrizio Bernardini
Rome, February 2001
(I need to check to which AGC Block II versions and AGC software versions this compilation is pertaining to.)
NASA Office of Logic Design
A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.
Apollo Guidance Computer (AGC) Schematics
https://klabs.org/history/ech/agc_schematics/index.htm
Apollo Guidance and Navigation
Apollo 15, CMC software package "Colossus 3"
CMC Data Cards
Delco Electronics, A Division of General Motors
Milwaukee, Wisconsin, April 1971
Apollo Guidance and Navigation
Apollo 15, LGC software package "Luminary 1E"
LGC Data Cards
Delco Electronics, A Division of General Motors
Milwaukee, Wisconsin, April 1971
Ref.
Ref.
Ref.
Ref.

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