Global description of the IBM 2075 CPU

1.The functional units of the IBM 2075 CPU

Diagram based on figure 7, 8 and 50 in ref.2 and descriptions in ref.1 Figure 1 Versatility In the diagram of figure 1 is shown a possible configuration context of an IBM 2075 CPU. It illustrates how data is exchanged between the CPU and the external devices via the six I/O channels and the various control units. The CPU was also able to facilitate the data exchange between devices via the I/O channels. Programs and data were made resident by transferring them from disk or tape memory to core memory (Main Memory or Large Capacity Storage). The diagram illustrates that the IBM 360-75 with its peripheral control equipment was able to handle a lot of I/O devices and had sophisticated arithmetic capabilities. The IBM 360-75 was part of a family of IBM 360 mainframes and was designed to support business and scientific applications. Major units of the CPU In figure 1 the three major units can be distinguished, each with their functional units: the Bus Control Unit (BCU); the Instruction Preparation Unit (I-Unit) and the Instruction Execution Unit (E-Unit). But the tangle of connections between the functional units has been left out to preserve the overview. Only the connections are shown to fetch instructions and fetch & store operands. The connections between the functional units consisted of control lines and data paths. The control lines sprang from the operation decoders to the various functional units to control the execution by these units and to various gates. These control lines were fixed. The data paths were in many cases variable and were determined by the settings of the various gates which were controlled by the operation decoders which translated instructions into control signals. Most gates are not shown in this diagram. Also not shown in the diagram are the sequencers. These circuits caused the various required actions to be executed in particular sequences, often across multiple CPU cycles. Together with the control signals from the operation decoders, they determined the data movements within the CPU. Test registers The MCW (Maintenance Control Word) register and the FLT (Fault Location Testing) register were test registers for maintenance and testing. The MCW register was part of a circuit to check on the integrity of the functional units which were responsible for error checking in the CPU or in a selected I/O channel. The FLT register was used for running diagnostic tests on the CPU circuitry. In case of a CPU hardware failure, a diagnostic program could be run which involved the use of test words to check specific responses from various circuits. The FLT register would then contain information for identifying the circuit responsible for the failure. Translation of instructions into Control Words. The CPU instructions were fetched from the main memory via the instruction buffers A and B into the I Unit Operation (IOP) Register. An instruction consisted of an Op Code, which dictates what the CPU should do, and an address, which denoted where the operand, the object to which the Op Code applied, can be found in main memory or CPU registers. The decoders are marked with a red outline. These translated the Op Code (operation code) into a string of binary control signals, which was called a Control Word. From the IOP register, the Op Code was distributed to the other operation registers. All these operation registers were used to provide the input for the operation decoders. The execution of an instruction was somewhat layered; it was controlled by various operation decoders. The IOP, BOP, BR1 field and ER1 field decoders were used to execute the preparation of the instruction. The EOP and LCOP decoders were used for the actual execution of the instruction. Hardwired The IBM 2075 CPU was hardwired. It meant that all operation decoders were equipped with fixed logic circuitry to translate a particular Op Code into a Control Word. As a result, the whole instruction set of about 170 instructions was laid down in the logic circuitry of the various decoders. The eight bits Op Code allowed for a maximum number of 256 instructions. Microcoded If the CPU would have been microcoded then each of the decoders would need to retrieve the Control Words from a special storage inside the CPU, called a control store. The Op Code would then have been used as an address word to fetch a Control Word from the Control Store. Such a Control Store would have allowed for managing the instruction set and for implementing upgrades. However, the translation process from OP Code to Control Word would have been more complex and would have taken more time to execute, which would have put a penalty on the CPU's performance. Diagram based on ref.6, figure 4 Figure 2 The basic concept of the CPU The basic concept of the Central Processing Unit (CPU) is shown in the small diagram above. The CPU contained the facilities for addressing main storage, for fetching or storing information, for arithmetic and logical processing of data, for sequencing instructions in the desired order, and for initiating the communication between storage and external devices. The system control section provided the normal CPU control that guided the CPU through the functions necessary to execute the instructions. While the physical make-up of the control section in the various models of the System 360 might have been different, the logical function remained the same. The result of executing a valid instruction was the same for each IBM 360 model. The CPU provided 16 general registers for fixed-point operands and 4 registers for floating-point operands. Implementation of these registers was realized in special circuitry, in a local storage unit, or in a separate area of main storage. In each case, the address and functions of these registers are identical. Source code - Compiler - Machine code The program instructions and data were put into the main memory from devices like tapes and disks via the I/O channels. These programs and data had to be put in machine code first to enable the CPU to process them. The machine code contained the CPU instructions and operands in binary codes. These programs in machine code were obtained by translating the programs, which were written in a user programming language called the source code, into machine code. This translating process was done by a program called a compiler, which was residing in the main memory during the translation process. The machine code was stored in the main memory when immediate execution was required or in other types of memory like the LCS or disks awaiting execution. The memory management capabilities of the operating system (RTOS/360) allowed for an efficient execution of machine code by swapping the code between memory types of long access times and the main memory with short access times, which were compatible with the CPU processing speed.

2.The instruction set of the IBM 2075 CPU

text The extensions of the instructions BC and BCR The Branch Instructions BC and BCR, in which various conditions are tested, each constitute a group of instructions to cover the various conditions. Therefore, the R1 field in the instruction formats RR and RX has been used to accommodate 4-bit extension codes of the 8-bit Op Code. Based on ref.7 and 8 Figure 3 Diagram based on ref.2, figure 5 and ref.7 Diagram based on ref.7 Figure 4 text text

3.Some basic concepts of the IBM 2075 CPU

Diagram based on ref.2, figure 33, 51, 52, 54 and 55 Figure 5 The sequence for preparing the instructions and the operands and the execution sequence were done simultaneously. It enabled the CPU to virtually spend all its time on the execution of instructions to produce the end results. It was the task of the Instruction Preparation Unit (I-Unit) to keep the E-Unit busy and keep track of all its operations to make the proper preparations in time. The preparation sequence was determined by a fixed set of instructions. There were, however, branches in the sequence to jump to instructions to anticipate various conditions which required alternative flows in the preparations sequence. The execution sequence, on the other hand, was determined by the instructions received by the Operation Registers of the E-unit. text Diagram based on ref.2, figure 11 Figure 6 The Program Status Word Register (PSW) The Program Status Word (PSW) Register was instrumental for the operation of the CPU. The PSW consisted of 8 bytes and 8 parity bits. The first 5 bytes of the PSW contained the information to create a situational awareness for the CPU. The information enabled the CPU to anticipate and respond to conditions from inside and outside its system domain. Interrupts and condition codes of internal functional units and of peripheral systems are examples of this kind of information. The last 3 bytes of the PSW contained the instruction counter (IC). The IC kept track of the memory address of the next instruction to be executed in a program. The IC kept track of the "to-do list" of the CPU, so to speak. The PSW, containing the IC, enabled the CPU to run down the "to-do list", taking into account the circumstances. Multitasking The IBM 2075 CPU was fast. Because the response time of peripheral systems serving the end-users could be 100 000 times longer than a typical CPU cycle time, the CPU was able to do many jobs virtually simultaneously. The CPU could in fact only process one instruction at a time. But by processing instructions of various jobs sequentially, the CPU could give the impression that it served all end-users simultaneously. Developments of IBM's Operating Systems resulted in an advanced usage of the PSW register to make jumps between a large number of programs possible. These operating systems incorporated some kind of interrupt handler to keep track of the handling of the various programs and store the content of the CPU registers after the current execution of an instruction had been finished first before the CPU had to jump to an instruction of another program. When the CPU had to switch back to a program, all the CPU registers, including the PSW register, were reloaded to enable the CPU to continue executing the program from the point it left the program.

Acronyms BCU Bus Control Unit BOP B Operation CPU Central Processor Unit EOP E Unit Operation IOP I Unit Operation LCOP Last Cycle Opreration LCS Large Capacity Storage VFL Variable Field Length MCC Mission Control Center MLA Multiplex Line Adapter RTOS Real Time Operating System References Introduction to IBM System/360 Architecture (For students) International Business Machines Corporation, 1967 White Plains, New York IBM Field Engineering Manual of Instruction 2075 Processing Unit - Volume 1 Comprehensive Introduction Functional Units IBM Systems Development Division, Product Publications Kingston, New York, December 1965 IBM Field Engineering Manual of Instruction 2075 Processing Unit - Volume 2 Storage Bus Control Instruction Preparation FLT, Logout, MCW Interrupts IBM Systems Development Division, Product Publications Kingston, New York, December 1965 IBM Field Engineering Manual of Instruction 2075 Processing Unit - Volume 3 Fixed Point I Execute Branch Floating Point Variable Field Length IBM Systems Development Division, Product Publications Kingston, New York, January 1966 IBM Field Engineering Manual of Instruction 2075 Processing Unit - Volume 4 Special features Power Supply and Control Appendix IBM Systems Development Division, Product Publications Kingston, New York, March 1966 IBM System/360 Principles Of Operation 8th edition of A22-6821-6 IBM Data Processing Division New York, September 1968 360 Assembly/360 Instructions https://en.wikibooks.org/wiki/360_Assembly/360_Instructions IBM System/360 Reference Data on Machine Instructions A foldable consultation card containing a summary of the specifications about the IBM 360 machine instructions, also known as the Green Card.

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