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IBM 360/75 system configuration
Backup arrangement
Configuration of an IBM 360/75 computer as selected by NASA for the Apollo mission support.
In this diagram is also shown how the Mission Operational Computer (MOC) was connected to a Dynamic Standby Computer (DSC). In this configuration the DSC was running the same jobs as the MOC but would not send data to the CCATS and to the Display & Control System. In case the MOC would fail, the DSC could take over swiftly.
The connection between the MOC and the DSC via the Channel-to-Channel Adapter (CCA) was used to establish an MOC-DSC pair out of the five available mainframes. It was used for transferring all the allocated storage from MOC to DSC to enable the DSC to duplicate MOC's work.
In case the DSC became the MOC, then the MOC became the DSC. If the problem with the previous MOC could be fixed quickly, the computer pair was maintained as well as the switching of roles. There was, however, always a third computer kept in reserve. In the case the original MOC had to be put out of commission for some time, the DSC, which had become the MOC, had to be paired up with the reserve computer, which then became the new DSC.
Note to the reader:
I am not sure whether the DSC obtained the data from the System Select Unit (SSU) via the MOC's Selector Channel or from the SSU directly. My guess would be from the SSU directly; it would make sense to duplicate the operational environment of the MOC as much as possible and have the peripheral equipment of the DSC doing the same jobs as that of the MOC as much as possible.
IBM 2075 CPU
The CPU was divided into three units:
1. the Bus Control Unit (BCU);
2. the Instruction Preparation Unit (I-Unit);
3. the Instruction Execution Unit (E-Unit).
The categories of functional units for each CPU unit are represented in the diagram.
In the diagram the Program Status Word Register (PSW register) of the I-Unit has been mentioned separately from the category "Registers". The 8 byte long PSW contains the 3 bytes long Instruction Counter and a total of 40 bits of data fields containing all kinds of status and control information which were instrumental for operating the CPU.
To a large extent the three units were operating independently and simultaneously. These units reflected the three distinct tasks which could be executed simultaneously to enhance the efficiency of the CPU. The units were logically interlocked to prevent them from overrunning each other.
The actual execution of an instruction which resulted in the requested end product was done by the E-unit.
The I-unit was responsible for fetching the instructions and fetching the operands, in fact collecting all the information the E-unit needed to just execute an instruction.
The BCU was taking care of all the required traffic between the CPU and the external devices.
The various decoders in the I-Unit and the E-Unit were translating the various operation codes (the instructions) into control signals which were sent to the appropriate functional units and to gates to set up the required data paths for actual execution of the instructions.
The instructions and the data were fetched from the Main Memory, where they were kept in storage as machine code. The machine codes were produced by a compiler or assembler program which had converted the user program, which was written in a high-level programming language, into machine code. This conversion process also included the breakdown of the high-level language instructions into a sequence of instructions (in machine code) which could be understood and executed by the CPU.
Compilers and assemblers were residing in the Main Memory or/and in the LCS.
A set of instructions which can be processed by a CPU is an integral part of its design. An instruction set is in fact laid out in the CPU decoders, which translate the instructions into control signals. Compilers and assemblers are provided with a library of all the available CPU instructions, which are used to convert the user program into machine code instructions. Since compilers or assemblers have to use a CPU to do their job, it is the CPU which is actually doing the conversion and is in fact used to generate its own input to execute the user program.
The instruction set of the CPU 2075 contained about 170 instructions.
The CPU 2075 was hardwired and not microcoded to maximize its processing speed.
The IBM 2075 CPU and its system context are briefly discussed in more detail on a separate page.
CPU memory
The CPU had access to up to four IBM 2365 units of 256 kbyte Processor Storage, a total of 1 MByte of storage. Data were stored in eight-byte words. So a total of 128 000 words could be stored in the main memory.
Two IBM 2361 Large Capacity Storage (LCS), with a capacity of 2 MByte each, could be added as a 4 MByte (512 000 words) extension of the Processor Storage.
The LCS also acted as a buffering device for exchanging data and programs with the IBM 2314 disk drives.
OS/360 and RTOS/360
The Operating System of an IBM 360 was residing on disks or tapes.
The mainframes needed to produce real-time data for the MCC to operate properly. For that purpose the OS/360 had to be adapted. OS/360 was an operating system for batch processing. For real-time applications a more sophisticated approach was required with regard to handling interrupts and tasks. IBM had developed an extension of the OS/360, the RTOS/360, the Real Time Operating System/360, to meet NASA's demands. Many features had been incorporated into this RTOS/360 to enhance the performance of the CPU and core memory, to introduce a Real-Time I/O Control System, to increase system reliability, to enhance task and data management and to improve the operator's monitoring and management utilities.
I/O Channels
The CPU 2075 had seven I/O channels. At least one of these seven must be used as a multiplexer channel and the other ones as a so-called selector channel. The multiplexer channel was suitable to be shared by various low-speed devices like printers, card readers and teletypes. A selector channel was suitable for high-speed devices like disk drives. It operated in the burst mode, meaning that it served one I/O device at a time. A selector channel could be subdivided into a maximum of eight subchannels; a total of 256 I/O devices could be addressed.
In this diagram tape drives are connected to the selector subchannels of the IBM 2870, which also contained the multiplexer subchannels.
In the diagram it is shown that for Channel 1 one subchannel was used to send data to other MCC systems and one subchannel was used to exchange data with disk drives.
The IBM 2701 data adapter unit provided a rapid demand response interface to the digital display (D.TV) in the MOCR and the RTCC.
The bidirectional exchange of data between the CPU and other MCC systems was provided through the Multiplexer Channel at apparently a lower data rate. Nevertheless, real-time acceptance and transmission of large amounts of data and control information could be accomplished through the use of the IBM 2902 Multiplex Line Adapter (MLA).
The IBM Storage Channel was an attachment to the IBM 2860-2 Selector Channel. It provided the capability of high-speed data transfer between storage locations in the main memory and the LCS. This storage channel enabled swapping of data and programs from low-speed storage to high-speed main processor storage and vice versa to use the high-speed CPU as efficiently as possible.
Using the storage channel was part of an usual strategy to organize storage types according to their performance. It was important that the operating system was able to anticipate the CPU's data and program routine demands; these data were often kept in storage in low-performance storage devices. Data traffic was well choreographed by the operating system to have data retrieved and transferred all the way up in the hierarchy of storage types right on time for processing according to a scheme as shown in the picture below. The CPU output was then transferred down in the hierarchy of storage types.
A selector channel could also be used to exchange data with another CPU.
Large Core Storage Support
One of the features of RTOS/360 was the improved management of the Large Capacity Storage (LCS). The LCS could be operated in three modes of operation to increase the performance of the IBM 360/75:
- Using the LCS for job shop operation management, which comprised various tasks:
- Using the LCS as an assembler work space instead of disks or tapes to improve assembler execution time;
- Using the LCS instead of main memory as work storage for compilers to allow larger compilations to be performed in main memory;
- Placing job control information on the LCS to increase job throughput;
- Using the LCS as a system residence device for nonresident (resident on disk or tape) operating system programs.
- Using the LCS as an addressable extension of main memory to be able to run larger application packages
- Using the LCS as a data funnelling device as depicted in the picture above. The RTOS/360 played a pivotal role in managing data swapping in the memory hierarchy chain to keep up with the CPU's information demand and to keep it busy to use the CPU as efficiently as possible.
The storage channel illustrates that the LCS could be used in two storage modes:
- as an extention of the CPU main memory in which data flows between the BCU and the LCS;
- as a data swapping device in the memory hierarchy. In that case the storage channel is used to enable the LCS to operate as an intermediate storage device between main memory and other storage devices via the selector channels.
Both modes could be used simultaneously and in various levels of usage, depending on the demand. The 2nd storage mode is very suitable for processes which rquires much data traffic between the CPU and various storage devices, as in the case of admistrative applications. The 1st storage mode is very suitable for fast and extensive processing of large amounts of data and in which far less data traffic is required between the CPU and various storage devices, as in the case of scientific applications.
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